Formal Verification

Formal verification is the process of checking whether a design satisfies some requirements. It is a critical element in the development of today’s complex digital designs. Hardware complexity growth continues to follow Moore’s Law, but verification complexity is even more challenging. Formal verification can be helpful in proving the correctness of systems such as: cryptographic protocols, combinational circuits, digital circuits with internal memory, and software expressed as source code. It is widely acknowledged as the major bottleneck in design methodology: Up to 70 percent of the design development time and resources are spent on functional verification.